Introducing the Phenom II 940
Deneb is finally here.
The original 65nm Phenom took its sweet time to market, and frankly, underwhelmed us compared to Intel's Penryn.
The TLB bug did not help.
AMD must have pulled out all the stops in bringing the "K10.5" aka Deneb as quickly as possible, but it was still later than everyone (except Intel) would have liked.
The Phenom II 940 - and the Phenom II 920 - are the first two 45nm Deneb processors that are being released by AMD - and AMD is finally hitting the clock speeds it was originally intending for the 65nm parts, with the Phenom II 920 coming in at 2.8GHz and the Phenom II 940 running at 3.0GHz.
Deneb is finally here.
The original 65nm Phenom took its sweet time to market, and frankly, underwhelmed us compared to Intel's Penryn.
The TLB bug did not help.
AMD must have pulled out all the stops in bringing the "K10.5" aka Deneb as quickly as possible, but it was still later than everyone (except Intel) would have liked.
The Phenom II 940 - and the Phenom II 920 - are the first two 45nm Deneb processors that are being released by AMD - and AMD is finally hitting the clock speeds it was originally intending for the 65nm parts, with the Phenom II 920 coming in at 2.8GHz and the Phenom II 940 running at 3.0GHz.
Ok, so what's different between the Phenom X4 and the Phenom II?
Geometry shrink to 45nm (from 65nm)
L3 shared cache increased to 6MB (from 2MB)
L3 cache 2 cycles faster than on previous Phenom
increased DRAM bandwidth
cores flush L1+L2 caches to L3 on halt to save power
path based indirect branch prediction
double the bandwidth for in-core probing
larger load/store and floating point buffering
reduced missed buffer lifetime
improved LOCK pipelining
floating point register-to-register MOV improvements
What does all of the above boil down to?
faster, larger L3 cache
more memory bandwidth
slightly faster core
Now for the technical specifications:
AMD Phenom II X4 920: 2.8GHz (14x200) multiplier-locked
AMD Phenom II X4 940 BE: 3.0GHz (15x200) multiplier-unlocked
45nm DSL SOI (silicon on insulator) technology
approx. 758M transistors
approx. 258mm2 die size
max case temp of 62'C
L1 cache: 64KB code + 64KB data per core (512KB total)
L2 cache: 512KB unified code/data per core (2MB total)
L3 cache: 6MB shared unified code/data cache
dual 64-bit memory channels can be ganged to 128 bits
Memory Controller: Supports up to DDR2-1066 and DDR3-1800 up to 17.1GB/sec
one HT3.0 link, 1.8GHz 16 bit in / 16 bit out, up to 14.4GB/sec
940 pin grid array
Vcore between 0.875-1.5V
Max 125W TDP
made in Fab 36, Dresden, Germany
Geometry shrink to 45nm (from 65nm)
L3 shared cache increased to 6MB (from 2MB)
L3 cache 2 cycles faster than on previous Phenom
increased DRAM bandwidth
cores flush L1+L2 caches to L3 on halt to save power
path based indirect branch prediction
double the bandwidth for in-core probing
larger load/store and floating point buffering
reduced missed buffer lifetime
improved LOCK pipelining
floating point register-to-register MOV improvements
What does all of the above boil down to?
faster, larger L3 cache
more memory bandwidth
slightly faster core
Now for the technical specifications:
AMD Phenom II X4 920: 2.8GHz (14x200) multiplier-locked
AMD Phenom II X4 940 BE: 3.0GHz (15x200) multiplier-unlocked
45nm DSL SOI (silicon on insulator) technology
approx. 758M transistors
approx. 258mm2 die size
max case temp of 62'C
L1 cache: 64KB code + 64KB data per core (512KB total)
L2 cache: 512KB unified code/data per core (2MB total)
L3 cache: 6MB shared unified code/data cache
dual 64-bit memory channels can be ganged to 128 bits
Memory Controller: Supports up to DDR2-1066 and DDR3-1800 up to 17.1GB/sec
one HT3.0 link, 1.8GHz 16 bit in / 16 bit out, up to 14.4GB/sec
940 pin grid array
Vcore between 0.875-1.5V
Max 125W TDP
made in Fab 36, Dresden, Germany
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